UNIMICRON TECHNOLOGY CORP.

The present disclosure provides a circuit board with an embedded chip, which includes a dielectric layer, a first circuit layer, a chip, a conductive connector, and an insulating protection layer. The first circuit layer includes at least one first trace in the dielectric layer. The chip is in the dielectric layer and adjacent to the first trace, where the chip includes a plurality of chip pads at an upper surface of the chip. The conductive connector is on the upper surface of the chip and on the first circuit layer, where a lower surface of the conductive connector contacts at least one chip pad of the chip pads and an upper surface of the first trace. The insulating protection layer is on the chip, the first circuit layer, and the conductive connector, where the insulating protection layer contacts the upper surface of the chip.

A circuit board device for transmitting signals at a frequency of 50 GHz to 300 GHz is provided. The circuit board device includes an insulating portion, first and second interlayer conduction structures passing through the insulating portion, a first reference layer, and a second reference layer. The first interlayer conduction structure defines a signal path and includes a first pillar including first end portions and a first central section. The first thickness of the first end portions is greater than the second thickness of the first central section. The first and second reference layers are located on top and bottom surfaces of the insulating portion and surround the first interlayer conduction structure. Two opposite second end surfaces of the second interlayer conduction structure are respectively connected to the first reference layer and the second reference layer to define a ground path surrounding the signal path.

A circuit board, including a first dielectric material, a second dielectric material, a third dielectric material, a fourth dielectric material, a first external circuit layer, a second external circuit layer, a conductive structure, a first conductive via, and multiple second conductive vias, is provided. The first conductive via at least passes through the first dielectric material and the fourth dielectric material, and is electrically connected to the first external circuit layer and the second external circuit layer to define a signal path. The second conductive vias pass through the first dielectric material, the second dielectric material, the third dielectric material, and a part of the conductive structure, and surround the first conductive via. The second conductive vias are electrically connected to the first external circuit layer, the conductive structure, and the second external circuit layer to define a ground path, and the ground path surrounds the signal path.

Disclosed is a package structure including a circuit board, a co-packaged optics (CPO) substrate, an application specific integrated circuit (ASIC) assembly, a glass interposer, an electronic integrated circuit (EIC) assembly, a photonic integrated circuit (PIC) assembly, and an optical fiber assembly. The CPO substrate is configured on the circuit board, and the ASIC assembly is configured on the CPO substrate. The glass interposer is configured on the CPO substrate and includes an upper surface, a lower surface, a cavity, and at least one through glass via (TGV). The EIC assembly is configured on the upper surface of the glass interposer and electrically connected to the glass interposer. The PIC assembly is configured in the cavity of the glass interposer and electrically connected to the glass interposer. The optical fiber assembly is configured on the lower surface of the glass interposer and optically connected to the PIC assembly.

A vapor chamber structure includes a first flexible substrate, a second flexible substrate, a spacer, a flexible sealing member, and a working fluid. The first flexible substrate includes a first organic material layer, a first copper foil layer, and a first capillary structure layer. The second flexible substrate includes a second organic material layer, a second copper foil layer, and a second capillary structure layer. The first copper foil layer, the first capillary structure layer, the spacer, the second copper foil layer, and the second capillary structure layer are retracted by a distance relative to the first and second organic material layers to form a space. The first and second organic material layers and the flexible sealing member define a sealed chamber. The working fluid is disposed in the sealed chamber and located among the first and second capillary structure layers and grooves of the spacer.

A substrate structure including a dielectric substrate, an adhesion promotion layer (APL), a conductive material, at least one dielectric layer and at least one pad. The dielectric substrate has an upper surface and a lower surface opposite to each other, and at least one through-hole passing through the dielectric substrate and connected to the upper surface and the lower surface. The APL is disposed on the upper surface, on the lower surface, and on an inner wall of the through-hole of the dielectric substrate. The conductive material fills the through-hole to define at least one conductive through-hole. The dielectric layer is disposed on the APL and has at least one opening exposing the conductive through-hole. A diameter of the opening is greater than a diameter of the conductive through-hole. The pad is disposed in the opening, extends onto the dielectric layer, and electrically connected to the conductive through-hole.

A load control probe device includes a probe module, a load sensor and a controller. The load sensor is connected to the probe module and used to measure the load data of the probe module, and the controller is connected to the probe module and the load sensor. A load control method, applicable for a probe module, includes: measuring, by a load sensor, load data of a probe module along a first direction, controlling the probe module to move along the first direction while simultaneously determining whether the load data meets a load setting value, and stopping the probe module from moving along the first direction and starting to control the probe module to perform signal detection when determining that the load data meets the load setting value.

A substrate structure includes a first substrate and a second substrate. The first substrate includes a first glass plate and at least one first conductive via penetrating the first glass plate. The second substrate includes a second glass plate and at least one second conductive via penetrating the second glass plate. The second substrate is connected to the first substrate. The second glass plate is bonded to the first glass plate through chemical bonding force and defines a chemical bonding contact surface with the first glass substrate. The at least one second conductive via is bonded to the at least one first conductive via through metal diffusion and defines at least one metal bonding contact surface with the at least one first conductive via.

An electronic packaging structure including a first circuit structure, a second circuit structure and at least one electronic device is provided. The first circuit structure includes a bottom conductive plate having at least one cavity. The first circuit structure is disposed on the second circuit structure. The first circuit structure and the second circuit structure are electrically connected to each other. The electronic device is disposed on the second circuit structure. The electronic device is disposed corresponding to the cavity of the first circuit structure.

A package structure includes a package substrate, an application specific integrated circuit (ASIC), a plurality of optoelectronic assemblies, and a plurality of organic interposers. The ASIC is disposed on the package substrate and electrically connected to the package substrate. The optoelectronic assemblies are separately disposed on the package substrate and surround the ASIC. Each of the plurality of optoelectronic assemblies includes an electronic integrated circuit (EIC), a photonic integrated circuit (PIC), and a plurality of hybrid bonding pads. The EIC is bonded to the PIC through the plurality of hybrid bonding pads. The plurality of organic interposers are separately disposed on the package substrate and surround the ASIC. The optoelectronic assemblies are electrically connected to the package substrate through the plurality of organic interposers.