EMEMORY TECHNOLOGY INC.

A SONOS type non-volatile memory includes a memory cell array. The memory cell array includes a memory cell area and a non-memory cell area. The connection relationship between SONOS memory cells in the memory cell area are specially designed, and the memory cell array is divided into multiple sections. When the erase action is performed, only one section in the memory cell array is erased, but the other sections are not erased. Furthermore, isolation transistors are provided in the non-memory cell area to isolate the well lines and the bit line. Consequently, the SONOS memory cells can be operated normally.

An erasable programmable non-volatile memory cell includes a well region, a first gate structure, a second gate structure, a first merged doped region, a second merged doped region and a lightly doped drain region. The first merged doped region is located beside a first side of the first gate structure. The lightly doped drain region is located beside a second side of the first gate structure and a first side of the second gate structure. The second merged doped region is located beside a second side of the second gate structure. The first merged doped region, the first gate structure and the lightly doped drain region are collaboratively formed as a select transistor. The lightly doped drain region, the second gate structure and the second merged doped region are collaboratively formed as a floating gate transistor.

A sense amplifier is provided. The sense amplifier includes first through third transistors, a bias circuit, and a voltage coupling circuit. The first transistor is coupled between a first power terminal and a first node. The second transistor is coupled between the first and second nodes, and has a gate receiving a reference voltage. The third transistor is coupled between the first and third nodes, and has a gate receiving a data voltage. The bias circuit couples the second and third nodes to a second power terminal. The voltage coupling circuit is coupled between the first node and the gate of the second transistor, and provides a first voltage to the gate of the second transistor. The first voltage is negatively correlated to a voltage at the first node. The gate of the second transistor has a resistor-capacitor loading smaller than that of the gate of the third transistor.

A memory read out circuit includes a sensing module, an output module, and a voltage boost unit. The sensing module is configured to sense a data stored in a memory cell to generate an output data signal according to a first supply voltage. The output module includes buffers and configured to output the output data signal stably. The voltage boost unit is configured to provide the first supply voltage to at least one of the buffers before the sensing module begins to sense the data, and provide a second supply voltage greater than the first supply voltage to the at least one of the buffers when the sensing module senses the data so as to raise a reading speed of the memory read out circuit.

A power supplying circuit and an associated switch controller for a non-volatile memory are provided. When the sector erase is performed, the voltage stress withstood by the switching transistors in the power supplying circuit is lower than the maximum voltage stress. In addition, the voltage stress withstood by all transistors in the switch controller is lower than the maximum voltage stress. In other words, when the sector erase is performed, all switch controllers and all switching transistors in the power supplying circuit can be operated normally. In addition, an erase voltage is provided to a specified sector of the array structure, so that all memory cells in the specified sector are erased into the erase state.

A memory device and a method for controlling a verification voltage of a memory device are provided. The method includes: determining a bit count of data bits verified in one verification cycle to be K according to electrical characteristics of a memory sector of the memory device, wherein K is a positive integer; controlling a charge pump circuit of the memory device to start detecting the verification voltage and start pulling up the verification voltage at a beginning time point of a present verification cycle of the memory sector; controlling the charge pump circuit to stop pulling up the verification voltage at a verification time point of the present verification cycle in response to the verification voltage reaching a predetermined level; and after the verification time point of the present verification cycle, using the verification voltage to verify K data bits written into the first memory sector.

An antifuse-type non-volatile memory cell includes a select transistor, a following transistor and a capacitor. The first drain/source terminal of the select transistor is connected with a bit line. The gate terminal of the select transistor is connected with a word line. A first drain/source terminal of the following transistor is connected with a second drain/source terminal of the select transistor. A gate terminal of the following transistor is connected with a following line. A second drain/source terminal of the following transistor is connected with a first terminal of the capacitor. A second terminal of the capacitor is connected with an antifuse control line.

A level shifter includes a cross-coupled circuit, a differential pair circuit, a NOT gate and a pulling device. The NOT gate receives an input signal and generates an inverted input signal. The cross-coupled circuit is connected to a first node and a second node. The cross-coupled circuit receives a first supply voltage. The voltage at the second node is used as an output signal. The differential pair circuit is connected to the first node and the second node. The differential pair circuit receives a ground voltage, the input signal and the inverted input signal. The pulling device is connected to the second node. The pulling device receives an enable signal. When the enable signal is not activated, the output signal is maintained at a specified logic level. When the enable signal is activated, the output signal changes with a change of the input signal.

A voltage booster includes a charge pump, a boost control circuit, a bandgap circuit, a voltage divider, a bandgap buffer, and a reference control circuit. The charge pump generates a pumped voltage according to an input power voltage. The boost control circuit generates an adjustment signal for controlling the charge pump according to a charge pump reference voltage and a feedback voltage of the pumped voltage. The bandgap circuit generates a bandgap voltage according to the pumped voltage. The voltage divider generates an input power reference voltage according to the input power voltage. The bandgap buffer generates a bandgap reference voltage according to the bandgap voltage. The reference control circuit generates the charge pump reference voltage according to the input power reference voltage before the bandgap circuit becomes ready, and generates the charge pump reference voltage according to the bandgap reference voltage after the bandgap circuit is ready.

A memory program control circuit includes a main counter, N registers, N DFFs, an update control unit, a group counter, and a write control unit. The main counter increments a main counter value according to a clock signal. The N registers store N bits to be written into a memory. The update control unit updates the N DFFs with the data stored in the N registers sequentially as the main counter value increments, and a write buffer is updated by a bit stored in a corresponding DFF as the DFF is updated. The group counter increments a group counter value each time a DFF is updated with a bit of a first type, and generates a group write enable signal when the group counter value reaches M, thereby having the write control unit perform a group write operation upon the memory.