Adeia Semiconductor Bonding Technologies Inc.

Techniques for stacking multiple semiconductor dies or active layers vertically to achieve higher density and shorter interconnections, often utilizing through-silicon vias (TSVs) or other vertical conductive paths like through-hole electrodes.

Methods for temporarily attaching a wafer or substrate to a carrier for thinning, dicing, or other processing, followed by controlled debonding, often using light-sensitive resins, temporary adhesives, or roughened interfaces.

Development of novel materials and designs for bonding, sealing, and underfill applications, focusing on improving mechanical integrity, electrical performance, and preventing defects like cracks or delamination in chip-to-chip connections.

Methods and structures for integrating and enclosing electronic components into compact, multi-functional modules, often involving embedded components, multi-layer substrates, and electromagnetic shielding for performance and miniaturization.

Inspection and testing methods specifically designed for wafers before, during, or after bonding processes, including verification of bonding surfaces, alignment, and defect detection in multi-wafer or stacked die assemblies.

Integrated solutions for dissipating heat generated by high-density semiconductor devices within the package, including embedded cooling structures, cold plates, and optimized fluidic channels.

Novel materials and processes for forming low-resistance electrical contacts and interconnects within semiconductor devices, including selective deposition, silicidation, and barrier layers for improved performance and scaling.

Packaging technologies where bare dies are embedded within a mold compound or substrate cavity, and then interconnected using redistribution layers (RDLs) for fan-out or compact integration, often avoiding through-silicon vias in the chips themselves.

Combining different types of functional chiplets (e.g., compute, memory, I/O, optical, power, biological) into a single package or system, often to optimize performance, power, or cost by leveraging specialized components.

Focuses on the physical design, materials, and manufacturing processes for individual memory cells, including transistor structures, interconnects, and multi-layered (3D) architectures to enhance density and performance.

The design and manufacturing of integrated circuits that combine optical and electronic components, particularly for high-speed data communication between processors and memory.

Innovations in the internal design of individual light-emitting diode chips or packages, focusing on semiconductor layer arrangements, electrode configurations, reflective elements, and light extraction features.

Materials and processes for hermetic encapsulation, conformal coating, optical chip sealing, and stretchable conductors for electronic and optoelectronic devices.

Novel electrical connection methods within or between package components, including through-glass vias (TGVs), backside contacts, and optimized redistribution layers for improved signal and power integrity.

Techniques and apparatus for electrically testing semiconductor devices, integrated circuits, or wafers during manufacturing or post-assembly, including built-in self-test (BIST) and contact reliability assessment.

Methods and materials used to construct robust and protective enclosures for electronic devices, focusing on structural integrity, impact resistance, thermal dissipation, and specialized material properties for enhanced durability.

Advanced techniques for forming and optimizing gate dielectrics, work function layers, and other dielectric layers within transistor structures to improve performance, reliability, and scaling.

Optical systems and components specifically designed for head-mounted displays, augmented reality (AR) glasses, and virtual reality (VR) headsets, focusing on image projection, waveguide integration, and display durability.

LED devices and display systems designed to emit or utilize light across different spectral ranges, including visible and invisible light, or to create specific illumination patterns and immersive lighting experiences.

Focuses on advanced pixel architectures, often involving vertical stacking (3D) or silicon-on-insulator (SOI) structures, to improve performance, density, or functionality of photodiodes, transistors, and floating diffusion regions within image sensor pixels.

Image sensors tailored for specific advanced functionalities beyond basic image capture, such as high dynamic range (HDR) imaging, single-photon detection, auto-focus, or distance measurement (LiDAR), often incorporating specialized pixel designs or processing.

Techniques and structural designs for assembling multiple display modules or panels to create a larger, continuous display with minimized visible seams, uniform light emission, and robust mechanical integrity.

Optical structures and lens designs that improve light extraction efficiency from LED dies and modules, including diffractive films, micro-lens arrays, reflectors, and color-conversion layers.

Techniques and systems for precisely measuring electrical or electromagnetic properties of materials or components, often involving specialized resonators, waveguides, or multi-range measurement systems to ensure accuracy.

Manufacturing processes and material compositions for creating electronic circuits on flexible or conformable substrates, enabling novel form factors, enhanced durability, and new applications beyond rigid PCBs.

Integration of various sensor types (e.g., thermal, strain) or display components directly onto semiconductor substrates or within device architectures for compact and high-performance systems.

Processes involving chemical and mechanical forces to planarize surfaces (CMP) or wet chemical treatments for cleaning, etching, or material removal, often utilizing specialized compositions, nozzles, or fluid management systems.